Multipath receiver of a spread spectrum communication system with dynamic matched filter and efficient signal combiner

ABSTRACT

A receiver employed in a communication system, for detecting, tracking and combining the various significant components of a multipath fading signal spanned over several symbol periods, consists of a plurality of signal register arrays, a block reference signal creator, a plurality of matched filters, a signal combiner, and a controller. The signal register arrays generates a plurality of moving sections of the received signal with one of the signal register array coupled to the received signal and each one of the rest signal register arrays coupled to its previous signal register array. At beginning of a communication section, the block reference signal creator generates a plurality of sections of a reference signal and holds these sections for a certain amount of time. During normal message transmission, the block reference signal creator generates a plurality of identical sections of the reference signal and holds the section for a symbol period, then generates the next identical section of the reference signal and holds the section for a symbol period. And repeat the processing. Each matched-filter is for finding the correlation between a section of the received signal and a section of the reference signal. The signal combiner is for combining the components from matched filters together. The controller is for monitoring the signals from all matched filters and signal combiners, extracting necessary information, and generating various control signals.

FEDERALLY SPONSORED RESEARCH

[0001] Not Applicable

SEQUENCE LISTING OR PROGRAM

[0002] Not Applicable

FIELD OF THE INVENTION

[0003] The invention is generally related to the receiver of acommunication system. More particularly the invention is related toapplying dynamic matched filters for detecting and tracking thecomponents of a multipath signal spanned over several symbol periods ina radio link of a direct sequence spreading spectrum communicationsystem and combining these components efficiently.

BACKGROUND OF THE INVENTION

[0004] In a wireless communication system, especially in a mobilecommunication system, fading occurs from times to times. Buildings,mountains, and foliage on the transmission path between a transmitterand a receiver can cause reflection, diffraction, and scattering on apropagating electromagnetic wave. The electromagnetic waves reflectedfrom various large objects, travel along different paths of varyinglengths. If there is an obstacle with sharp irregularities on thetransmission path, the secondary waves resulting from the obstructingsurface are present around the obstacle. Also if there are smallobjects, rough surfaces, and other irregularities on the transmissionpath, scattered waves are created. All these waves will interact witheach other and result in multipath fading.

[0005] Under some environments such as in many metropolitan areas, thereis no line-of-sight signal. The received signal is a multipath-fadingsignal from reflection, scattering, and diffraction. Statistically noany particular component of the multipath-fading signal is stable for arelatively long period of time and significant stronger than the restcomponents in a fairly large region. In order to provide service tothese areas with good quality, all these major components of themultipath-fading signal have to be combined in some way so that onaverage the combined signal will be more stable and stronger than eachcomponent.

[0006] Before any attempting to combine the components of amultipath-fading signal, one has to identify all the significantcomponents. This would require that all the significant components mustbe recognizable. That is, a transmitted symbol must be different fromany of its neighbor symbols within the multipath-spanned range so that adelayed version of a transmitted symbol will be not mistaken as adifferent symbol.

[0007] A direct sequence spread spectrum system can naturally provide away to distinguish the neighbor transmitted symbols and therefore allthe significant components of a multipath-fading signal arerecognizable. This is due to the fact that the delayed versions of thetransmitted pseudo-noise (PN) signal have poor correlation with theoriginal PN signal.

[0008] As IP originated messages are more and more popular,packet-switched communication system is more and more common. In apacket-switched communication system, a received package could come fromtotal different source than the one before and the one after, andtherefore generally there is no any relation between two adjacentpackets. When transmission rate is very high, in order to reduce thecapacity loss of communication system and obtain multipath informationbefore the information loses its meaning, one could prefer to usematched-filter instead of correlator.

[0009] However, the regular matched filters do not work well. For aregular matched filter, the reference signal is fixed. In a directsequence spreading spectrum communication system, the reference signalis changing all the time. Some modifications around the matched filterhave to be made so that the matched filters are able to detect thevarious components of a multipath fading signal spanned over severalsymbol periods even though the reference signal is changing all thetime.

[0010] The common method to combine several components of amultipath-fading signal consists of several steps. First, let thereceived signal pass a delay line with taps. The length of delay lineshould be long enough that the section of received signal captured bythe delay line is equal or larger than range spanned by the multipathfading signal. Second, depending on the relative positions of thesignificant components, the several corresponding taps are selected.Third, the signal from each of selected taps is weighted by a differentweight and is aligned properly by phase. And finally all the weightedsignals are added together.

[0011] The common method of combinations has some drawbacks in a directcommunication system.

[0012] First, when a multipath-fading signal spans for a large range andwhen the data rate is high, the above approach could consume a lot ofhardware. In a direct sequence communication system, there are 64 chipsin each symbol period and a multipath signal spans about 4 symbolperiods. If one takes 4 samples in each chip, the delay line willconsist of 4×64×4=1024 memory elements. Further suppose there are atmost two significant components, in order to be able to select the twocorresponding taps, two selective devices are needed with each one isconnected to the 1024 memory elements. The selective devices consume alot of hardware.

[0013] Second, a separate circuit could be needed to monitor eachsignificant component. In order to keep good communication quality, onehas to constantly monitor the information related to all the significantpaths and adjust the weight, phase, and position associated with eachsignificant component. But in a direct sequence spreading spectrumcommunication system, the signal from a selective tap does not directlyprovide the necessary information about that corresponding path. Adespreading circuit has to be used to despread the signal of a selectivetap and then the information about a corresponding path could beextracted.

[0014] In order to avoid huge selective devices and a plurality ofdespreading circuits, one perhaps prefers to despread each significantcomponent by common despreading circuit first then combine thesecomponents together.

[0015] Based on previous discussions, it would be desirable to provide amechanism for a receiver of a spreading spectrum communication system todespread all significant multipath components by a bank of matchedfilters, extract the related information from these despreadedcomponents, and combine all the despreaded significant componentsefficiently.

OBJECTIVES OF THE INVENTION

[0016] The first idea behind the invention is based on the observationthat all the significant components of a multipath-fading signal spanover a limited range. A bank of matched filters is able to capture allthese significant components if each of them can capture the componentsover a different portion of the limited range.

[0017] The second idea behind the invention is based on the observationthat for the purpose of signal combination, it is enough to delay somesamples of a despreaded signal instead of the despreaded signal itselffor some amount of time.

[0018] The primary objective of the invention is to provide a method fora receiver of a direct sequence spreading spectrum communication systemto detect and track the various components of a multipath fading signalspanned over several symbol periods with a bank of matched filters.

[0019] Another objective of the invention is to provide method ofdelaying the sampled values of a despreaded signal efficiently.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in andconstitute a part of the specification, depict the preferred embodimentsof the present invention, and together with the description, serve toexplain the principle of the invention. In the figures, like referencenumerals refer to the same or similar elements.

[0021]FIG. 1 illustrates the first embodiment of applying a bank ofdynamic matched filters and a signal combiner in a receiver of acommunication system.

[0022]FIG. 2 illustrates the first implementation of the referencesignal creator in a FIG. 1.

[0023]FIG. 3 illustrates the second implementation of the referencesignal creator in a FIG. 1.

[0024]FIG. 4 illustrates the signal combiner in a FIG. 1.

[0025]FIG. 5 illustrates the second embodiment of applying a dynamicmatched filter and a signal combiner in a receiver of a communicationsystem.

[0026]FIG. 6 illustrates the signal combiner in a FIG. 6.

[0027]FIG. 7 illustrates the first implementation of the delay line usedin FIG. 4 and FIG. 6.

[0028]FIG. 8 illustrates the second implementation of the delay lineused in FIG. 4 and FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Detailed description of the preferred embodiments is providedherein. The embodiments illustrate dynamic matched filter bank, signalcombiner, and their applications in a receiver of a communication systemby way of examples, not by way of limitations. It is to be understoodthat it could be easy for those skilled in the art to modify theembodiments in many different ways. Therefore, specific detailsdisclosed are not to be interpreted as limitations, but rather as basesfor the claims and as representative bases for teaching one to employthe present invention in virtually any appropriately detailed system,structure or manner.

[0030] We assume that there are at most M significant multi-pathcomponents and the multipath signal spans over less than L symbols. Wefurther assume that all the significant components of a multipath signalemerging during the communication section will not appear t₀ secondearlier than the first significant component detected at the beginningof a communication section.

[0031] Also we assume that there are N chips in each symbol period,there are K samples in each chip. For simplicity, in the example, we letM=2, L=3, N=10, and K=4.

[0032] Let's denote the frequency of sampling clock by f_(s), thefrequency of the X times of the frequency of the sampling clock byf_(X), the frequency of chip clock by f_(c), and the frequency of thesymbol clock by f_(sym). Correspondingly, the period of sampling clockis denoted by T_(s) seconds, the period of a clock X times of thefrequency of the sampling clock by T_(X) seconds, the period of a chipby T_(c) seconds, and period of a symbol by T_(sym) seconds.

[0033]FIG. 1 shows the first embodiment of applying a bank of dynamicmatched filters and a signal combiner in a receiver of a communicationsystem.

[0034] For simplicity, these matched filters are called dynamic matchedfilters for their reference signals are different from the time to time.

[0035] The received signal S_(in) is fed into signal register array 105₁, which consists of a plurality of signal shift registers with thefirst signal shift register coupled to the received signal S_(in) andeach of the rest signal shift registers cascaded to its previous signalshift register. There is a tapped output signal from each signal shiftregister. The received signal S_(in) and all these tapped output signalsare sent to matched-filter 115 ₁. The tapped output signal from the lastsignal shift register of the signal registers array 105 ₁ is also fed tothe first signal shift register of signal register array 105 ₂. Thesignal register array 105 ₂ has same number of signal shift registers asthe signal register array 105 ₁, with each signal shift registercascaded to its previous signal register. Also there is a tapped outputsignal from each signal shift register. All these tapped output signalsare sent to the matched filter 115 ₂.

[0036] There are totally L signal register arrays from 105 ₁ to 105_(L), with one signal register array cascaded by its previous one. Allthese signal register arrays have exactly the same structures and havesame number of tapped output signals. Corresponding to a segment of thereceived signal S_(in) in one symbol period, the tapped output signalsfrom each signal register array, are sent to a corresponding matchedfilter from 115 ₁ to 115 _(L). The output signals from a signal registerarray form a moving section of received signal S_(in) in sampledversion. Each section size is corresponding to a symbol period. Thetapped output signals from all these L signal register arrays from 105 ₁to 105 _(L), form a big moving section of received signal S_(in) insampled version. The big moving section has a size corresponding to Ltimes the symbol period.

[0037] A shifting clock drive all the signal shift registers of eachsignal register array. In most case, the shifting clock is the samplingclock.

[0038] For simplicity, we further assume that at the beginning of acommunication section, there is an identification sequence of L symbolsor LN chips for initial estimation of the parameters related to amultipath fading signal. We also assume all these L symbols have samephase. When there are more than L symbols needed for such estimation,either more hardware or some trade-off may be required. When there areless than L symbols needed for such estimation, only portion of thehardware will be used and the unused portion could be disabled.

[0039] When a communication starts, the reference signal creator 110generates L symbols of the identification sequence with each symbol fora corresponding matched filter. The reference signal creator 110 willhold these symbols until LT_(sym−) t₀ seconds after a first component ofa multipath signal has been detected. Therefore the output of eachmatched filter is the correlation between a section of theidentification sequence and a corresponding section of received signalS_(in). When the summation of the output signals from these matchedfilters has big signal strength, there is good probability that acomponent of a multipath signal exists. During initialization, all thecomponents spanned over less than L symbol periods of the multipathsignal will be caught up.

[0040] LT_(sym−) t₀ seconds after the first component of a multipathsignal has been detected, the reference signal creator 110 will generateL identical reference symbols with one for a corresponding matchedfilter every symbol period. The reference symbol of any of the L matchedfilters changes from one symbol period to another.

[0041] Corresponding to L signal register arrays, there are L matchedfilters from 115 ₁ to 115 _(L). Each of these matched filters 115 _(i),i=1, . . . L, is to find the correlation between its reference signaland its input signal from a corresponding signal register array. Theoutput of matched filters 115 _(i) is denoted by MF₁, with i=1, . . . L.

[0042] The controller 120 extracts information from various devices suchas matched filters and signal combiner, and provides various controlsignals to block reference signal generators and signal combiner.

[0043] The information collected from the outputs of all these matchedfilters are used for not only updating the information about thecurrently tracked significant components such as the signal strengths,phases, and positions, but also looking for new significant components.A significant component of the multipath-fading signal emerged afterinitialization, will be detected by the controller 120 from the outputsignal of each matched filter. When the output from a particular matchedfilter is significant at a same position for continuous several symbolperiods, there is a good probability that a new significant componenthas emerged.

[0044] When the significant components of the multipath signal isshifted to one side or another side, the controller 120 will properlyadjust the instant to update the reference signal creator 110 so that nosignificant component will not be detected.

[0045] The signal combiner 125 combines the various significantcomponent of a multipath signal together. Taking the output signal ofsignal combiner 125 as its input signal, the decision circuit 130, makesa decision on the transmitted symbol.

[0046]FIG. 2 shows the first implementation of the reference signalcreator 110 in a FIG. 1.

[0047] There are L block reference signal generators 140 ₁ to 140 _(L),with each one under control of different control signals from thecontroller 120.

[0048] When a communication starts, under the control of the controller120, the L block reference signal generators 140 ₁ to 140 _(L) generatethe L symbols of the identification sequence and hold these symbolsuntil LT_(sym−) t₀ seconds after the first component of a multipathsignal has been detected. Then, a normal communication starts. Under thecontrol of the controller 120, the L block reference signal generators140 ₁ to 140 _(L) generate L identical reference symbols every symbolperiod. The controller 120 has control on these reference signalgenerators on when to update their output symbols.

[0049]FIG. 3 shows the second implementation of the reference signalcreator 110 in a FIG. 1.

[0050] There is a block reference signal generator 150 and L registers155 ₁ to 155 _(L).

[0051] When a communication starts, under the control of the controller120, the block reference signal generator 150 generates L symbols of theidentification sequence and each of the L registers 155 ₁ to 155 _(L)will catch one of the L symbols. The L registers 155 ₁ to 155 _(L) willhold these symbols until LT_(sym−) t₀ seconds after the first componentof a multipath signal has been detected. Then, the block referencesignal generator 150 will generate a new symbol at the interval of everysymbol period and each of the L registers 155 ₁ to 155 _(L) will catchthe same new symbol simultaneously. The controller 120 has control onthe block reference signal generator 150 on when to generate a newsymbol and the L registers 155 ₁ to 155 _(L) on when to catch theirinput symbols.

[0052]FIG. 4 shows the signal combiner 125 in a FIG. 1.

[0053] From the assumption that there are at most M possible significantcomponents of a multipath signal, there are M identical mechanisms eachfor capturing each one of the M components. For simplicity, only thefirst one will be explained.

[0054] The mechanism for capturing the first component, consists of ademultiplexer 205 _(A), a sampling device 210 _(A), a delay line 215_(A), and a complex multiplier 220 _(A).

[0055] The demultiplexer 205 _(A) takes the output signals of allmatched filters 115 ₁ to 115 _(L), denoted by MF₁ to MF_(L) as its inputsignals. A control signal from the controller 120 makes thedemultiplexer 205 _(A) pass a desired matched filter output signal to asampling device 210 _(A).

[0056] Another control signal from the controller 120 makes the samplingdevice 210 _(A) take samples from the output of demultiplexer 205 _(A)at proper instants. The sampling device 210 _(A) could consist of Dflip-flops and be driven by a sampling clock f_(s).

[0057] The output of sampling device 210 _(A) is fed to a delay line 215_(A). Under the control signals from the controller 120, a proper delayis inserted. The output of the delay line 215 _(A) is multiplied at themultiplier 220 _(A) by a complex weight signal from the controller 120.The complex weight signal has a magnitude proportional to the averagesignal strength of the first component and a phase compensating forfirst component.

[0058] The output signals from all M multiplier 220 _(A) to 220 _(B) areadded at adder 225. The summation will be sent to the decision circuit130 in FIG. 1.

[0059] The output signals of all matched filters are also fed to adder230. During the initialization, the threshold logic circuit 235 checksif the output signal of adder 230 has a signal strength stronger than athreshold and flags if a component of a multipath signal has beendetected. Both the output signals of adder 230 and threshold logiccircuits 235 are sent to controller 120 for extracting the informationrelated to the component at the beginning of a communication section.

[0060]FIG. 5 shows the second embodiment of applying a dynamic matchedfilter and a signal combiner in a receiver of a communication system.

[0061] The received signal S_(in) and the signal register array 305 ₁ to305 _(L) in FIG. 5 are same as the received signal S_(in) and the signalregister array 105 ₁ to 105 _(L) in FIG. 1 respectively.

[0062] The output signals from each of the L signal register arrays 305₁ to 305 _(L) are connected to the demultiplexer 310. A control signalfrom controller 325 makes the demultiplexer 310 select output signalsfrom each of signal register arrays by turn. The demultiplexer 310 hasto work at a frequency at least L time of the shifting clock of thesesignal registers. The output of demultiplexer 310 is connected to thematched filter 320.

[0063] There is a block reference signal generator 315. At the initialstage of a communication section, the block reference signal generator315 will generate L reference symbols of the identification sequencewith each reference symbol corresponding to a signal register array.After LT_(sym−) t₀ seconds of the moment when the first component of amultipath signal is detected, the block reference signal generator 315will generate one symbol or N chips every symbol period. The output ofthe block reference signal generator 315 is connected to the matchedfilter 320.

[0064] The matched filter 320 is used to find the correlation valuebetween the current section of the reference signal and a correspondingsection of the received signal represented by the output signals of asignal register array. It works at least L times as fast as the shiftingclock of the L signal register arrays 305 ₁ to 305 _(L)

[0065] The output signal of matched filter 320, denoted by MF, is sentto both controller 325 and signal combiner 330.

[0066] The signal combiner 330 is used to combine the up to Msignificant multipath signals together. The output from signal combiner330 is sent to decision circuit 335 to make a final decision on whichsymbol is transmitted.

[0067]FIG. 6 shows the signal combiner 330 in a FIG. 5.

[0068] As in FIG. 4, among the M exactly same mechanisms for capturing Mpossible paths, only the first one will be explained.

[0069] The output of matched filter 320 is fed to a sampling device 410_(A). The sampling device 410 _(A) could consists of D flip-flops and bedriven by a clock with a frequency at least L times of the shiftingclock f_(s). A control signal from the controller 325 makes the samplingdevice 410 _(A) to take samples from the output of matched filter 320 atproper instants.

[0070] The output of sampling device 410 _(A) is fed to a delay line 415_(A). Under the control signals from the controller 325, a proper delayis inserted. The output of the delay line 415 _(A) is multiplied atmultiplier 420 _(A) by a complex weight signal from the controller 325.The complex weight signal has a magnitude proportional to the averagesignal strength of the first component and a phase compensating forfirst component.

[0071] The output signals from all M multiplier 420 _(A) to 420 _(B) areadded at adder 425. The summation will be sent to the decision circuit335 in FIG. 5.

[0072] The output signal from the matched filter 320 is also fed to L−1memory devices 430 ₁ to 430 _(L−1). These devices work at a frequency ofL times the shifting frequency of signal registers in the signalregister array 305 ₁ to 305 _(L). The L−1 output signals from L−1 memorydevices 430 ₁ to 430 _(L−)1 and the output signal MF from matched filterare sent to an adder 435. The output signal of the adder 435 will besent to the controller 325, which will check the signal at properinstants and find out if there is a significant component.

[0073]FIG. 7 shows the first implementation of the delay line 215 inFIG. 4 and the delay line 415 in FIG. 6.

[0074] There are K−1=3 memory elements 510 ₁ to 510 ₃. The input signalis fed to the first memory elements 510 ₁ and each of the rest memoryelements is cascaded to its previous one. Sampling clock f_(s) drivesthese memory elements 510 ₁ to 510 ₃. They could be a plurality of Dflip-flops. Both the input signal and the outputs of memory devices 510₁ to 510 ₃ are sent to a selecting device 520.

[0075] Under a control signal from a controller, the selecting device520 selects one input signal from its K=4 input signals as its outputsignal.

[0076] There are another N−1=9 memory elements 530 ₁ to 530 ₉. Theoutput signal of the selecting device 520 is fed to the first memoryelements 530, and each of the rest memory elements is cascaded to itsprevious one. These memory elements are driven by a chip clock f_(c).They could be a plurality of D flip-flops. Both the input signal to thefirst memory element 530 ₁ and the output signals of memory devices 530₁ to 530 ₉ are sent to a selecting device 540.

[0077] Under a control signal from a controller, the selecting device540 selects one input signal from its N=10 input signals as its outputsignal.

[0078]FIG. 8 shows the second implementation of the delay line 215 inFIG. 4 and the delay line 415 in FIG. 6.

[0079] Various significant components, after matched filter, are all inone symbol period. Therefore, the maximum delay is no more than a symbolperiod or N·K samples. The relative position of any multipath componentcan be represented by no more than ┌log₂(N·K)┐ binary bit. When N=10 andK=4, we obtain ┌log₂(N·K)┐=┌log₂(40)┐=6, where ┌x┐ denotes the smallestinteger larger or equal to x. Any delay d in the right range could beunique expressed by

d=n ₀ ·T _(s) +n ₁·(2T _(s))+n ₂·(4T _(s))+n ₃·(8T _(s))+ . . . +n_(k)·(2^(k) T _(S))

Where k=┌log₂ (N·K)┐−1=5 and n ₁=1 or 0 for i=0, . . . , k.

[0080] The delay line in FIG. 8 consists of ┌log₂(N·K)┐ memory elements605 to 655 and ┌log₂(N·K)┐ demultiplexers 610 to 660. The memoryelements could consist of D flip-flops. Each of these ┌log₂(N·K)┐ memoryelements 605 to 655 is driven by different clock and therefore producesdifferent delay.

[0081] The control signals from a controller will make each of thedemultiplexers to select a proper input signal as its output andtherefore a desired delay will be generated.

[0082] Input signal is fed to the memory element 605 and thedemultiplexer 610. The memory element 605 is driven by the samplingclock f_(s). Depending on the value of n₀, different control signal willbe generated. When n₀=1, a control signal will let demultiplexer 610pass the output signal of the memory element 605; otherwise, the controlsignal will let demultiplexer 610 pass the input signal of the memoryelement 605.

[0083] The output signal of demultiplexer 610 is fed to the memoryelement 615 and demultiplexer 620. The memory element 615 is driven by aclock whose frequency is half of the sampling clock f_(s). Depending onthe value of n₁, different control signal will be generated. When n₁=1,a control signal will let demultiplexer 620 pass the output signal ofthe memory element 615; otherwise, the control signal will letdemultiplexer 620 pass the input signal of the memory element 615.

[0084] Similarly, the output signal of demultiplexer 620 is fed to thememory element 625 and demultiplexer 630 . The memory element 625 isdriven by a clock whose frequency is one-fourth of the sampling clockf_(s). Depending on the value of n₂, different control signal will begenerated. When n₂=1, a control signal will let demultiplexer 630 passthe output signal of the memory element 625; otherwise, the controlsignal will let demultiplexer 630 pass the input signal of the memoryelement 625.

[0085] In this way, the output signal of demultiplexer 650 (not shown inthe figure) is fed to the memory element 655 and demultiplexer 660. Thememory element 655 is driven by a clock whose frequency is 1/32 of thesampling clock f_(s). Depending on the value of n₅, different controlsignal will be generated. When n₅=1, a control signal will letdemultiplexer 660 pass the output signal of the memory element 655;otherwise, the control signal will let demultiplexer 660 pass the inputsignal of the memory element 655.

What is claimed is:
 1. A subsystem for detecting, tracking, andcombining the components of a multipath fading signal spanned overseveral symbol periods, comprising: a plurality of signal registerarrays, one of which is coupled to the received signal and each of therest of which is coupled to its previous signal register array, whereineach signal register array is for capturing a moving section of sampledversion of the received signal with the section size corresponding to asymbol period; a reference signal creator for generating a plurality ofsections of a reference signal with section size corresponding to asymbol period and each section updated from time to time; a plurality ofmatched filters, wherein each of the matched filters is for finding thecorrelation value between the current section of the received signalcaptured in a corresponding signal register array and a correspondingsection of the reference signal from the reference signal creator; and acontroller for extracting information from various devices and generatevarious control signals for various devices.
 2. A subsystem fordetecting, tracking, and combining the components of a multipath fadingsignal spanned over several symbol periods as in claim 1, wherein areference signal creator further comprises a plurality of blockreference signal generators with each generating a section of thereference signal and holding it for a certain amount of time, thengenerating the next section of the reference signal and holding it for acertain amount of time, and repeating the process.
 3. A subsystem fordetecting, tracking, and combining the components of a multipath fadingsignal spanned over several symbol periods as in claim 2, wherein acertain amount of time is a symbol period of time.
 4. A subsystem fordetecting, tracking, and combining the components of a multipath fadingsignal spanned over several symbol periods as in claim 2, wherein aplurality of block reference signal generators, each block referencesignal generator consists of a linear feedback shift register with afeedback logic to shift a plurality of chips at one time.
 5. A subsystemfor detecting, tracking, and combining the components of a multipathfading signal spanned over several symbol periods as in claim 1, whereina reference signal creator further comprises a block reference signalgenerator and a plurality of registers, with the block reference signalgenerator generating a different section of the reference signal for adifferent register and each register capturing a corresponding sectionof the reference signal at different moment.
 6. A subsystem fordetecting, tracking, and combining the components of a multipath fadingsignal spanned over several symbol periods as in claim 1, wherein areference signal creator further comprises a block reference signalgenerator and a plurality of registers, with the block reference signalgenerator for generating a section of the reference signal every certainamount of time and each register for capturing the same section of thereference signal.
 7. A subsystem for detecting, tracking, and combiningthe components of a multipath fading signal spanned over several symbolperiods as in claim 5, wherein the block reference signal generatorconsists of a linear feedback shift register with a feedback logic toshift a plurality of chips at one time.
 8. A subsystem for detecting,tracking, and combining the components of a multipath fading signalspanned over several symbol periods as in claim 1, further comprising asignal combiner, which is coupled to a plurality of matched filters, forcombining various components of a multipath signal together.
 9. Asubsystem for detecting, tracking, and combining the components of amultipath fading signal spanned over several symbol periods as in claim8, wherein a signal combiner further comprising a plurality ofdemultiplexers, each of which is coupled to the outputs of a pluralityof matched filters, each demultiplexer for selecting one of the outputsignals from the plurality of matched filters as its output signal; aplurality of sampling devices, each of which is coupled to the output ofa demultiplexer, each sampling device for taking a sample on the outputsignal of a corresponding demultiplexer; a plurality of delay lines,each of which is coupled to the output of a sampling device, each delayline for creating different amount of delay between its input signal andits output signal; a plurality of multipliers, each of which is coupledto the output of a delay line, each multiplier for weighting androtating a significant component of the multipath fading signal; and anadder circuit, which is coupled to the output of said plurality ofmultipliers, for combining the various significant components of themultipath fading signal together.
 10. A subsystem for detecting,tracking, and combining the components of a multipath fading signalspanned over several symbol periods as in claim 9, further comprising anadder coupled to a plurality of matched filters and a threshold logiccircuit, for adding the output signals from all matched filter togetherand checking if a significant component of the multipath fading signalhas been detected.
 11. A subsystem for detecting, tracking, andcombining the components of a multipath fading signal spanned overseveral symbol periods, comprising: a plurality of signal registerarrays, one of which is coupled to the received signal and each of therest of which is coupled to its previous signal register array, whereineach signal register array is for capturing a moving section of sampledversion of the received signal with the section size corresponding to asymbol period; a demultiplexer, which is coupled to each of signalregister arrays, for selecting a different section of the receivedsignal at different time; a block reference signal generator forgenerating a plurality of sections of a reference signal and generatinga section of a reference signal at a time with section sizecorresponding to a symbol period; a matched filter, which is coupled tothe output of the demultiplexer, for finding the correlation valuesbetween a plurality of sections of the received signal and a pluralityof sections of reference signal from the block reference signalgenerator; a controller for extracting information from various devicesand generate various control signals for various devices; and a signalcombiner, which is coupled to said matched filter, for combining varioussignificant components of the multipath fading signal together.
 12. Asubsystem for detecting, tracking, and combining the components of amultipath fading signal spanned over several symbol periods as in claim11, wherein a block reference signal generator comprises a linearfeedback shift register with a feedback logic to shift a plurality ofchips at one time.
 13. A subsystem for detecting, tracking, andcombining the components of a multipath fading signal spanned overseveral symbol periods as in claim 11, wherein a signal combiner furthercomprising: a plurality of sampling devices, each of which is coupled tothe matched filter, each sampling device for taking a sample on theoutput signal of the matched filter at different time; a plurality ofdelay lines, each of which is coupled to the output of a samplingdevice, each delay line for creating a certain amount of delay betweenits input signal and output signal; a plurality of multipliers, each ofwhich is coupled to the output of a delay line, each multiplier forweighting and rotating a significant component of the multipath fadingsignal; and an adder circuit, which is coupled to the output of saidplurality of multipliers, for combining the various significantcomponents of the multipath fading signal together.
 14. A subsystem fordetecting, tracking, and combining the components of a multipath fadingsignal spanned over several symbol periods as in claim 11, furthercomprising a plurality of cascaded memory devices driven by a clock witha frequency of a plurality times of the frequency of the sampling clockand an adder coupled to the tapped output signals of these memorydevices, for adding the tapped output signals together.
 15. A subsystemfor delaying a signal sample for variable amount of time comprises: aplurality of set of memory devices, with the memory devices in a sameset are driven by a same clock and the memory devices in different setsare driven by different clocks, for generating different amount ofdelays; a plurality of selecting devices, for selecting one signal asits output signal from its plurality of input signals; whereby aplurality of set of memory devices and a plurality of selecting deviceswork together to generate desired amount of delay.
 16. A subsystem fordelaying a signal sample for variable amount of time as in claim 15,wherein the memory devices in a same set are driven by a same clock, thememory devices in a set are driven by the sampling clock and the memoryin another set are driven by the chip clock.
 17. A subsystem fordelaying a signal sample for variable amount of time as in claim 15,wherein a plurality of sets of memory devices, each memory devicecomprises a plurality of D flip-flops.
 18. A subsystem for delaying asignal sample for variable amount of time as in claim 15, wherein aplurality of selecting devices, one of which is coupled to the samplingdevice and a corresponding set of memory device and each of rest coupledto the output signal of its previous selecting device and acorresponding set of memory device,
 19. A subsystem for delaying asignal sample for variable amount of time comprises: a plurality of setsof memory devices, with each set of memory devices driven by differentclocks, for generating different amount of delays; and a plurality ofdemultiplexers, each of which is coupled to the input port and outputport of a different memory device, each demultiplexer for selecting onesignal as its output signal from its two input signals; whereby aplurality of sets of memory devices and a plurality of selecting deviceswork together to generate a required delay.
 20. A subsystem for delayinga signal sample for variable amount of time as in claim 19, wherein eachset of memory devices driven by different clocks, each clock has afrequency half of the frequency of its previous clock.